I think you can load a 32 bit constant with 3 non-branching instructions, actually.
1) load 2nd following instruction
2) xor top 8 bits of value with constant
3) instruction with top 8 bits set so that the bottom 24 bits are ignored
I need to check the details of this, but it should work i'd think in 3 cycles and 12 bytes:
Update: something like (if setting 0 as a constant, we'd use different (hopefully shorter) instructions):
ldr r5, [pc, #4] // load contents of "whatever instruction" I probably got the syntax wrong...
eors r5, high_8_bits_of_value shl #24 // this will always have the zero flag clear, provided we're not setting 0
.word low_24_bits_of_value // note that this encodes as if zeroflag-set: some data-operation, one of and, eor, sub, rsb, add, adc, sbc or rsc
Last edited by Justin; 06-03-2012 at 02:51 PM.
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